DDR2 SDRAM memory chip, 256Mbit density, organized as 16Mx16 for a 16-bit data bus. Features a maximum clock rate of 800 MHz, 4 internal banks, and a 15-bit address bus. Packaged in an 84-pin FBGA with surface mount capability, operating at 1.8V with a maximum access time of 0.4 ns.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Samsung K4T56163QN-HCE7 technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 12.5 |
| Package Width (mm) | 7.5 |
| Seated Plane Height (mm) | 1.1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 256Mbit |
| Type | DDR2 SDRAM |
| Organization | 16Mx16 |
| Data Bus Width | 16bit |
| Maximum Clock Rate | 800MHz |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 4M |
| Maximum Access Time | 0.4ns |
| Density in Bits | 268435456bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 130mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 95°C |
Compliance
| Cage Code | 1542F |
| EU RoHS | Yes |
| HTS Code | 8542320024 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Samsung K4T56163QN-HCE7 Datasheet
Download the complete datasheet for Samsung K4T56163QN-HCE7 to view detailed technical specifications.
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