Synchronous SRAM chip, 36M bit density, featuring a 2M x 18 configuration with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 200 MHz, utilizing QDR data rate architecture. This surface-mount component is housed in a 165-pin FBGA package (17x15x0.95mm) with a 1mm pin pitch, operating at a typical supply voltage of 1.8V (1.7V-1.9V range) and supporting a 2-port, pipelined architecture.
Samsung K7R321882C-EC20T00 technical specifications.
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