Synchronous SRAM chip, 36M bit density, featuring a 2M x 18 configuration with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 200 MHz, utilizing QDR data rate architecture. This surface-mount component is housed in a 165-pin FBGA package (17x15x0.95mm) with a 1mm pin pitch, operating at a typical supply voltage of 1.8V (1.7V-1.9V range) and supporting a 2-port, pipelined architecture.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Samsung K7R321882C-EC20T00 technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.95
Seated Plane Height (mm)
1.3
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
20bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
200MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
700mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
2M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
1542F
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Samsung K7R321882C-EC20T00 Datasheet
Download the complete datasheet for Samsung K7R321882C-EC20T00 to view detailed technical specifications.
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