36-pin QFN EP surface mount clock generator with 2 outputs. Accepts crystal, LVCMOS, and LVPECL input logic levels, generating CML, CMOS, LVDS, and LVPECL output logic levels. Operates with clock input frequencies from 0.002MHz to 710MHz, with an output frequency up to 1417MHz. Features a 6x6x0.83mm QFN EP package with a 0.5mm pin pitch, suitable for operation between -40°C and 85°C. Supply voltage range is 1.71V to 3.63V.
PackageQFN EP
MountingSurface Mount
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Technical Specifications
Silicon Labs Si5324A-C-GM technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | QFN |
| Package/Case | QFN EP |
| Package Description | Quad Flat No Lead Package, Exposed Pad |
| Lead Shape | No Lead |
| Pin Count | 36 |
| PCB | 36 |
| Package Length (mm) | 6 |
| Package Width (mm) | 6 |
| Package Height (mm) | 0.83 |
| Seated Plane Height (mm) | 0.85 |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-220VJJD-7 |
| Number of Outputs per Chip | 2 |
| Input Logic Level | Crystal|LVCMOS|LVPECL |
| Output Logic Level | CML|CMOS|LVDS|LVPECL |
| Clock Input Frequency | 0.002 to 710MHz |
| Min Operating Supply Voltage | 1.71V |
| Max Operating Supply Voltage | 3.63V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 6SQ24 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Silicon Labs Si5324A-C-GM Datasheet
Download the complete datasheet for Silicon Labs Si5324A-C-GM to view detailed technical specifications.
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