SK hynix e-NAND is a product family featuring embedded NAND flash and an MMC controller. It integrates an intelligent controller for managing interface protocols, wear leveling, bad block management, garbage collection, and ECC. Designed to protect data from host sudden power-off failures, it is compatible with the JEDEC standard eMMC4.5 specification and is backward compatible with eMMC4.41. It supports features like HS200 mode, HPI, BKOPS, partitioning, secure TRIM, write protect functions, and health reporting.
Package153FBGA
Temp Range-25 to +85°C
Quick Jump:
Technical Specifications
SK Hynix H26M31001HPR technical specifications.
General
| Number of Terminals | 153 |
| Terminal Position | BOTTOM |
| JEDEC Package Code | R-PBGA-B153 |
| Number of Functions | 1 |
| Number of Words | 4294967296 |
| Number of Words Code | 4000000000 |
| Memory IC Type | FLASH |
| Density | 4GB |
| NAND Information | 1ynm 32Gb |
| Package Size | 11.5x13x0.8 |
| Package Type | 153FBGA |
| Compatibility | eMMC4.5 (Backward compatible to eMMC4.41) |
| Data Bus Width | 1 bit (default), 4 bits, 8 bits |
| Data Transfer Rate | Up to 200MB/s (HS200) |
| MMC I/F Clock Frequency | 0-200MHz |
| MMC I/F Boot Frequency | 0-52MHz |
| Operating Voltage - VCC (NAND) | 2.7 - 3.6V |
| Operating Voltage - Vccq (Controller) | 1.7 - 1.95 / 2.7 - 3.6V |
| Operating Temperature | -25 to +85°C |
| Storage Temperature (Non-operational) | -40 to +85°C |
| Sequential Read Performance | 130MB/s |
| Sequential Write Performance | 10MB/s |
| Active Power Consumption - Average Icc | 40mA |
| Active Power Consumption - Peak Icc | 80mA |
| Active Power Consumption - Average Iccq | 100mA |
| Active Power Consumption - Peak Iccq | 200mA |
| Low Power Mode (Standby) - Icc | 100uA |
| Low Power Mode (Standby) - Iccq | 30uA |
| Low Power Mode (Sleep) - Icc | 0A |
| Low Power Mode (Sleep) - Iccq | 30uA |
| Endurance - Total Bytes Written (TBW) | 2.4TB |
| HS200 Clock Timing - tPERIOD (Min) | 5ns |
| HS200 Clock Timing - Duty Cycle | 30-70% |
| HS200 Device Input Timing - tisu (Min) | 1.40ns |
| HS200 Device Input Timing - tIH (Min) | 0.8ns |
| High-speed Interface Timing - Clock Frequency (Data Transfer Mode) | 0-52MHz |
| High-speed Interface Timing - Clock High Time (Min) | 6.5ns |
| High-speed Interface Timing - Clock Low Time (Min) | 6.5ns |
| High-speed Interface Timing - Clock Rise Time (Max) | 3ns |
| High-speed Interface Timing - Clock Fall Time (Max) | 3ns |
| High-speed Interface Timing - Input Set-up Time (Min) | 3ns |
| High-speed Interface Timing - Input Hold Time (Min) | 3ns |
| High-speed Interface Timing - Output Delay Time (Max) | 13.7ns |
| High-speed Interface Timing - Output Hold Time (Min) | 2.5ns |
| High-speed Interface Timing - Signal Rise Time (Max) | 3ns |
| High-speed Interface Timing - Signal Fall Time (Max) | 3ns |
| Dual Data Rate Interface Timing - Clock Duty Cycle | 45-55% |
| Dual Data Rate Interface Timing - Output DAT Delay Time (Min) | 1.5ns |
| Dual Data Rate Interface Timing - Output DAT Delay Time (Max) | 7ns |
| Boot Partition Size | 4096KB |
| User Data Area Capacity | 3,909,091,328Bytes |
| Erase Group Size (ERASE_GROUP_DEF=0) | 512KB |
| Erase Group Size (ERASE_GROUP_DEF=1) | 512KB |
| Write Protect Group Size | 8MB |
| Read Timeout | 100ms |
| Write Timeout (CMD to write Done) | 500ms |
| Erase Timeout | 50ms |
| Force Erase Timeout | 3min |
| Discard Timeout | 600ms |
| Trim Timeout | 400ms |
| Secure Trim Timeout | 6s |
| Sanitize Timeout | 8min |
| Secure Erase Timeout | 6s |
| Initialization Timeout (CMD to Response) | 1s |
| 1st Initialization Timeout after Partitioning | 1s |
| PON Busy Time (Short) | 100ms |
| PON Busy Time (Long) | 1s |
| Initialization after PON (Short) | 180ms |
| Initialization after PON (Long) | 580ms |
| BKOP Exit Time by HPI | 100ms |
| Auto-BKOP Exit Time | 100ms |
| HPI Response Time | 100ms |
| CMD5 Sleep In Timeout | 2ms |
| Manufacturer ID (CID) | 90h |
| OEM/Application ID (CID) | 4Ah |
| Product Name (CID) | 4GB |
| Product Revision (CID) | 01h |
| Relative Card Address (RCA) Default Value | 0x0001 |
| Driver Stage Register (DSR) Default Value | 0x404 |
Compliance
| RoHS | Yes |
| REACH | Compliant |
| Military Spec | False |
| Standard | JEDEC eMMC4.5 |
Datasheet
SK Hynix H26M31001HPR Datasheet
Download the complete datasheet for SK Hynix H26M31001HPR to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.