CD54HC107F3A

Dual J-K Flip-Flop, CMOS, 60MHz, Neg-Edge Trigger, CDIP

Dual negative-edge triggered J-K flip-flops with reset, featuring CMOS technology and a maximum operating frequency of 60MHz. This integrated circuit offers a propagation delay of 255ns and operates within a supply voltage range of 2V to 6V. Designed for through-hole mounting in a CDIP package, it provides 5.2mA of output current at both high and low levels. The component supports a wide operating temperature range from -55°C to 125°C.

Frequency60MHz

PackageCDIP

MountingThrough Hole

PolarityNon-Inverting

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Technical Specifications

Texas Instruments CD54HC107F3A technical specifications.

General

Package/Case	CDIP
Clock Edge Trigger Type	Negative Edge
Contact Plating	Tin, Lead
Frequency	60MHz
High Level Output Current	-5.2mA
Lead Free	Contains Lead
Logic Function	JK-Type
Low Level Output Current	5.2mA
Max Frequency	60MHz
Max Operating Temperature	125°C
Min Operating Temperature	-55°C
Max Supply Voltage	6V
Min Supply Voltage	2V
Mount	Through Hole
Number of Bits	2
Number of Elements	2
Packaging	Rail/Tube
Polarity	Non-Inverting
Propagation Delay	255ns
Quiescent Current	4uA
Radiation Hardening	No
RoHS Compliant	No
Technology	CMOS
Turn-On Delay Time	255ns