32-bit ARM Cortex M3 RISC microcontroller featuring 80 MHz clock speed and 256KB Flash program memory. This surface-mount device offers 32KB RAM, 67 programmable I/Os, and 4 timers. Connectivity includes 2 I2C and 3 UART interfaces. Packaged in a 108-pin NFBGA (10x10x1.02mm) with 0.8mm pitch, it operates from 1.2V/3.3V and across a -40°C to 105°C temperature range.
PackageNFBGA
MountingSurface Mount
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Technical Specifications
Texas Instruments LM3S1811-EBZ80-C0T technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | NFBGA |
| Package Description | Plastic Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 108 |
| PCB | 108 |
| Package Length (mm) | 10 |
| Package Width (mm) | 10 |
| Package Height (mm) | 1.02 |
| Seated Plane Height (mm) | 1.36 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-219 |
| Family Name | Stellaris |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 80MHz |
| Maximum CPU Frequency | 80MHz |
| Device Core | ARM Cortex M3 |
| Program Memory Type | Flash |
| Program Memory Size | 256KB |
| RAM Size | 32KB |
| Number of Programmable I/Os | 67 |
| Core Architecture | ARM |
| Programmability | Yes |
| Number of Timers | 4 |
| Interface Type | I2C/SSI/UART |
| CAN | 0 |
| I2C | 2 |
| SPI | 0 |
| Ethernet | 0 |
| UART | 3 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.32|3.6V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 105°C |
| ADC Channels | 8 |
| Number of ADCs | Single |
Compliance
| Cage Code | 01295 |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Texas Instruments LM3S1811-EBZ80-C0T Datasheet
Download the complete datasheet for Texas Instruments LM3S1811-EBZ80-C0T to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.