32-bit ARM Cortex M3 RISC microcontroller featuring 128KB Flash program memory and 20KB RAM. This MCU operates at a maximum clock rate of 50 MHz and offers 33 programmable I/Os. It includes 3 timers and supports I2C, SSI, and UART interfaces. Packaged in a 48-pin QFN EP (Quad Flat No Lead Package, Exposed Pad) with a 7mm x 7mm footprint, it is designed for surface mounting and operates from -40°C to 105°C.
PackageQFN EP
MountingSurface Mount
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Technical Specifications
Texas Instruments LM3S1J16-EGZ50-C0 technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | QFN |
| Package/Case | QFN EP |
| Package Description | Quad Flat No Lead Package, Exposed Pad |
| Lead Shape | No Lead |
| Pin Count | 48 |
| PCB | 48 |
| Package Length (mm) | 7(Max) |
| Package Width (mm) | 7(Max) |
| Package Height (mm) | 0.95(Max) |
| Seated Plane Height (mm) | 1(Max) |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-220 |
| Family Name | Stellaris |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 50MHz |
| Maximum CPU Frequency | 50MHz |
| Device Core | ARM Cortex M3 |
| Program Memory Type | Flash |
| Program Memory Size | 128KB |
| RAM Size | 20KB |
| Number of Programmable I/Os | 33 |
| Core Architecture | ARM |
| Programmability | Yes |
| Number of Timers | 3 |
| Interface Type | I2C/SSI/UART |
| CAN | 0 |
| I2C | 2 |
| SPI | 0 |
| Ethernet | 0 |
| UART | 3 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.32|3.6V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 105°C |
| ADC Channels | 8 |
| Number of ADCs | Single |
Compliance
| Cage Code | 01295 |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Texas Instruments LM3S1J16-EGZ50-C0 Datasheet
Download the complete datasheet for Texas Instruments LM3S1J16-EGZ50-C0 to view detailed technical specifications.
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