N-channel enhancement mode power MOSFET featuring a 200V drain-source voltage and 8.5A continuous drain current. This single-element silicon transistor offers a low drain-source on-resistance of 400mΩ at 10V. Packaged in a TO-220NIS through-hole configuration with 3 pins and a tab, it has a typical gate charge of 17nC and input capacitance of 700pF. Maximum power dissipation is 30W, with an operating temperature range of -55°C to 150°C.
PackageTO-220NIS
MountingThrough Hole
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Technical Specifications
Toshiba 2SK2350(MATUS) technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | TO-220 |
| Package/Case | TO-220NIS |
| Package Description | Transistor Outline Package |
| Lead Shape | Through Hole |
| Pin Count | 3 |
| PCB | 3 |
| Tab | Tab |
| Package Length (mm) | 10 |
| Package Width (mm) | 4.5 |
| Package Height (mm) | 15 |
| Seated Plane Height (mm) | 15 + 5.6(Max) |
| Pin Pitch (mm) | 2.54 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Configuration | Single |
| Category | Power MOSFET |
| Channel Mode | Enhancement |
| Channel Type | N |
| Number of Elements per Chip | 1 |
| Maximum Drain Source Voltage | 200V |
| Maximum Gate Source Voltage | ±20V |
| Maximum Continuous Drain Current | 8.5A |
| Material | Si |
| Maximum Drain Source Resistance | 400@10VmOhm |
| Typical Gate Charge @ Vgs | 17@10VnC |
| Typical Gate Charge @ 10V | 17nC |
| Typical Input Capacitance @ Vds | 700@10VpF |
| Maximum Power Dissipation | 30000mW |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 150°C |
Compliance
| Cage Code | S0562 |
| HTS Code | 8541290095 |
| Schedule B | 8541290080 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Toshiba 2SK2350(MATUS) Datasheet
Download the complete datasheet for Toshiba 2SK2350(MATUS) to view detailed technical specifications.
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