Dual JK-Master-Slave Flip-Flop, positive-edge triggered, CMOS logic family. This surface-mount integrated circuit features two independent JK-Master-Slave flip-flop elements, each with two inputs and one output. Packaged in a 16-pin SOL (Small Outline IC) with gull-wing leads, it offers a 1.27mm pin pitch and operates within a temperature range of -40°C to 85°C.
PackageSOL
MountingSurface Mount
PolarityInverting/Non-Inverting
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Technical Specifications
Toshiba TC4027BFN(F,N,M) technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | SOP |
| Package/Case | SOL |
| Package Description | Small Outline IC (L Lead) |
| Lead Shape | Gull-wing |
| Pin Count | 16 |
| PCB | 16 |
| Package Length (mm) | 9.9 |
| Package Width (mm) | 3.9 |
| Package Height (mm) | 1.38 |
| Seated Plane Height (mm) | 1.75(Max) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Logic Family | 4000B |
| Logic Function | JK-Master-Slave Type |
| Process Technology | CMOS |
| Number of Elements per Chip | 2 |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Polarity | Inverting/Non-Inverting |
| Triggering Type | Positive-Edge |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | S0562 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Toshiba TC4027BFN(F,N,M) Datasheet
Download the complete datasheet for Toshiba TC4027BFN(F,N,M) to view detailed technical specifications.
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