Dual JK-type flip-flop IC featuring negative-edge triggering and two elements per chip. This CMOS logic device offers inverting/non-inverting outputs and operates within a -40°C to 85°C temperature range. Packaged in a 16-pin PDIP (Plastic Dual In Line Package) for through-hole mounting, it has a 2.54mm pin pitch and a maximum package length of 19.75mm.
PackagePDIP
MountingThrough Hole
PolarityInverting/Non-Inverting
Quick Jump:
Technical Specifications
Toshiba TC74HC112AP(HQ) technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | PDIP |
| Package Description | Plastic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 16 |
| PCB | 16 |
| Package Length (mm) | 19.75(Max) |
| Package Width (mm) | 6.4 |
| Package Height (mm) | 3.5 |
| Seated Plane Height (mm) | 4.15 |
| Pin Pitch (mm) | 2.54 |
| Package Material | Plastic |
| Mounting | Through Hole |
| Jedec | MS-001BB |
| Logic Family | HC |
| Logic Function | JK-Type |
| Process Technology | CMOS |
| Number of Elements per Chip | 2 |
| Number of Element Inputs | 2 |
| Number of Element Outputs | 1 |
| Polarity | Inverting/Non-Inverting |
| Triggering Type | Negative-Edge |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | S0562 |
| EU RoHS | No |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Toshiba TC74HC112AP(HQ) Datasheet
Download the complete datasheet for Toshiba TC74HC112AP(HQ) to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.