Field Programmable Gate Array (FPGA) featuring 1920 Configurable Logic Blocks (CLBs) and an estimated 1,000,000 system gates. Operates at a maximum clock frequency of 630 MHz with 17280 memory cells. This CMOS device utilizes a 256-pin, 17x17mm Fine-Pitch Ball Grid Array (FPBGA) package. Supports a nominal supply voltage of 1.2V, with a range of 1.14V to 1.26V. Designed for operation between 0°C and 85°C.
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| Max Operating Temperature | 85 |
| Number of Terminals | 256 |
| Min Operating Temperature | 0 |
| Terminal Position | BOTTOM |
| JEDEC Package Code | S-PBGA-B256 |
| Width | 17 |
| Length | 17 |
| Pin Count | 256 |
| Temperature Grade | OTHER |
| Supply Voltage-Nom | 1.2 |
| Supply Voltage-Min | 1.14 |
| Supply Voltage-Max | 1.26 |
| Number of Outputs | 173 |
| Clock Frequency-Max | 630 |
| Number of Inputs | 173 |
| RoHS | Yes |
| Eccn Code | EAR99 |
| Lead Free | Yes |
| HTS Code | 8542.39.00.01 |
| REACH | Compliant |
| Military Spec | False |
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