
Field Programmable Gate Array (FPGA) with 101,261 logic cells and 126,576 registers, built on 45nm process technology. Features 4824 Kbit RAM bits, 360 18x18 multipliers, and 180 dedicated DSP blocks. Offers 160 maximum user I/Os and 18 DLLs/PLLs. SRAM programmable with transceiver speeds up to 3.2 Gbps. Housed in a 225-pin Chip Scale Ball Grid Array (CSBGA) package, measuring 13x13x0.9mm with a 0.8mm pin pitch, suitable for surface mounting and operating between -40°C and 100°C.
Xilinx XC6SLX100-L1CSG225I technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | CSBGA |
| Package Description | Chip Scale Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 225 |
| PCB | 225 |
| Package Length (mm) | 13 |
| Package Width (mm) | 13 |
| Package Height (mm) | 0.9 |
| Seated Plane Height (mm) | 1.4(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 160 |
| Number of Registers | 126576 |
| RAM Bits | 4824Kbit |
| Device Logic Cells | 101261 |
| Process Technology | 45nm |
| Number of Multipliers | 360 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Dedicated DSP | 180 |
| Speed Grade | 1L |
| Device Number of DLLs/PLLs | 18 |
| Total Number of Block RAM | 268 |
| Cage Code | 68994 |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Download the complete datasheet for Xilinx XC6SLX100-L1CSG225I to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.