Field Programmable Gate Array (FPGA) with 14,579 logic cells and 18,224 registers, built on 45nm process technology. Features 576 Kbit RAM, 64 18x18 multipliers, and 32 dedicated DSP blocks. Offers 576 user I/Os and a transceiver speed of 3.2 Gbps. Packaged in a 900-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, with dimensions of 31x31x1.75mm and a 1mm pin pitch. Operates within a temperature range of 0°C to 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Xilinx XC6SLX16-2FGG900C technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 900 |
| PCB | 900 |
| Package Length (mm) | 31 |
| Package Width (mm) | 31 |
| Package Height (mm) | 1.75 |
| Seated Plane Height (mm) | 2.25 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 576 |
| Number of Registers | 18224 |
| RAM Bits | 576Kbit |
| Device Logic Cells | 14579 |
| Process Technology | 45nm |
| Number of Multipliers | 64 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 32 |
| Speed Grade | 2 |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 32 |
Compliance
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Xilinx XC6SLX16-2FGG900C Datasheet
Download the complete datasheet for Xilinx XC6SLX16-2FGG900C to view detailed technical specifications.
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