Field Programmable Gate Array (FPGA) with 24,051 logic cells and 30,064 registers, featuring 936 Kbit of RAM and 52 Block RAMs. This device utilizes 45nm process technology, offers 498 maximum user I/Os, and includes 38 dedicated DSP blocks and 76 18x18 multipliers. Operates with a 1.2V supply and supports transceiver speeds up to 3.2 Gbps. Packaged in a 676-pin Fine Pitch Ball Grid Array (FBGA) with a 1mm pin pitch, suitable for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Xilinx XC6SLX25-2FG676C technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 676 |
| PCB | 676 |
| Package Length (mm) | 27 |
| Package Width (mm) | 27 |
| Package Height (mm) | 1.73 |
| Seated Plane Height (mm) | 2.23 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAL-1 |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 498 |
| Number of Registers | 30064 |
| RAM Bits | 936Kbit |
| Device Logic Cells | 24051 |
| Process Technology | 45nm |
| Number of Multipliers | 76 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 38 |
| Speed Grade | 2 |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 52 |
Compliance
| Cage Code | 68994 |
| EU RoHS | No |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Xilinx XC6SLX25-2FG676C Datasheet
Download the complete datasheet for Xilinx XC6SLX25-2FG676C to view detailed technical specifications.
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