
Field Programmable Gate Array (FPGA) with 24051 logic cells and 30064 registers, featuring 936 Kbit of RAM and 76 dedicated 18x18 multipliers. This device operates on 45nm process technology, offering 226 user I/Os and 38 dedicated DSP blocks. It includes 52 Block RAMs and 6 DLLs/PLLs, with transceiver speeds up to 3.2 Gbps. The FPGA is housed in a 324-pin Chip Scale Ball Grid Array (CSBGA) package, measuring 15mm x 15mm x 0.9mm, designed for surface mounting. Operating temperature range is 0°C to 85°C.
Xilinx XC6SLX25-L1CSG324C technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | CSBGA |
| Package Description | Chip Scale Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 324 |
| PCB | 324 |
| Package Length (mm) | 15 |
| Package Width (mm) | 15 |
| Package Height (mm) | 0.9 |
| Seated Plane Height (mm) | 1.5(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | Spartan®-6 LX |
| Maximum Number of User I/Os | 226 |
| Number of Registers | 30064 |
| RAM Bits | 936Kbit |
| Device Logic Cells | 24051 |
| Process Technology | 45nm |
| Number of Multipliers | 76 (18x18) |
| Programmability | Yes |
| Transceiver Speed | 3.2Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 38 |
| Speed Grade | 1L |
| Device Number of DLLs/PLLs | 6 |
| Total Number of Block RAM | 52 |
| Cage Code | 68994 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Download the complete datasheet for Xilinx XC6SLX25-L1CSG324C to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.