EE PLD, 12ns, 256-Cell, CMOS, CPGA192, CERAMIC, PGA-192
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| Max Operating Temperature | 70 |
| Number of Terminals | 192 |
| Min Operating Temperature | 0 |
| Terminal Position | PERPENDICULAR |
| JEDEC Package Code | S-CPGA-P192 |
| Width | 45.15 |
| Length | 45.15 |
| Pin Count | 192 |
| Temperature Grade | COMMERCIAL |
| Supply Voltage-Nom | 5 |
| Supply Voltage-Min | 4.75 |
| Supply Voltage-Max | 5.25 |
| Clock Frequency-Max | 125 |
| Number of I/O Lines | 164 |
| RoHS | No |
| Eccn Code | EAR99 |
| Lead Free | No |
| HTS Code | 8542.39.00.01 |
| REACH | Compliant |
| Military Spec | False |
