Parallel NOR flash memory provides 8 Mbit of nonvolatile storage organized as 1,048,576 bytes or 524,288 words. The device operates from a single 2.7 V to 3.6 V supply for read, program, and erase operations. It supports top or bottom boot-block sector configurations, x8 or x16 data bus operation, and access times as fast as 70 ns. Sector erase, embedded program and erase algorithms, hardware reset, and Ready/Busy status signaling are supported. The product family is retired and not recommended for new designs.
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| Memory Size | 8Mbit |
| Organization | 1,048,576 x 8-bit or 524,288 x 16-bit |
| Memory Type | CMOS boot-sector flash memory |
| Supply Voltage | 2.7 to 3.6V |
| Access Time | 70 minimum speed gradens |
| Process Technology | 0.32µm |
| Sleep Mode Current | 200 typical at 5 MHznA |
| Standby Current | 200 typical at 5 MHznA |
| Read Current | 7 typical at 5 MHzmA |
| Program/Erase Current | 15 typicalmA |
| Sector Architecture | One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors in byte mode |
| Boot Block Configuration | Top or bottom boot block |
| Endurance | 1,000,000 minimumcycles/sector |
| Data Retention | 20 at 125 °Cyears |
| Package Options | 48-ball FBGA, 48-pin TSOP, 44-pin SO, Known Good Die |
| Status Pins | RY/BY# Ready/Busy, Data# Polling, toggle bits |
| Reset Pin | RESET# hardware reset |
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