A floating-point digital signal processor implements the SHARC architecture for high-performance signal-processing and embedded-control applications. The processor supports 32-bit fixed-point and 32-bit IEEE floating-point computation with a 25 ns instruction cycle at 40 MHz. On-chip SRAM provides low-latency program and data storage, while serial ports, an external port, and a host interface support system I/O. The device family includes ADSP-21061 and ADSP-21061L variants with different supply-voltage options.
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| Processor architecture | SHARC |
| Data format | 32 fixed-point and 32 IEEE floating-pointbit |
| Maximum clock frequency | 40MHz |
| Instruction cycle time | 25ns |
| Peak floating-point performance | 120MFLOPS |
| On-chip SRAM | 1Mbit |
| Serial ports | 2 synchronous serial ports |
| Host interface | Supported |
| External memory interface | External port |
| Processor class | Digital signal processor |
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