SHARC+ single-core digital signal processor provides 400 MHz maximum core operation with 640 kB of L1 SRAM and 256 kB of shared L2 SRAM. The processor supports 32-bit, 40-bit, and 64-bit floating-point processing, 32-bit fixed-point processing, and enhanced FIR/IIR accelerators. Integrated audio and control interfaces include full SPORTs with TDM and I2S modes, S/PDIF transmit and receive, ASRC pairs, Quad SPI, Octal SPI, I2C, UART, timers, GPIO, and DAI pins. The 120-lead LQFP_EP package measures 14 mm by 14 mm and is RoHS compliant. Orderable variants support 0°C to +110°C or –40°C to +125°C junction temperature ranges.
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| Core architecture | SHARC+ single core |
| Maximum core clock frequency | 400MHz |
| L1 SRAM | 640kB |
| L2 SRAM | 256kB |
| Floating-point support | 32, 40, 64bit |
| Fixed-point support | 32bit |
| Full SPORT interfaces | 8 with TDM and I2S modes |
| S/PDIF interfaces | 2 receive/transmit |
| ASRC pairs | 8 |
| Precision clock generators | 4 |
| Quad SPI interfaces | 2 |
| Octal SPI interfaces | 1 |
| I2C interfaces | 4 |
| UART interfaces | 2 |
| GPIO pins | 22 |
| DAI pins | 24 |
| ADC | 2-channel 12-bit housekeeping ADC |
| Core supply voltage | 0.95 to 1.05V |
| External I/O supply voltage | 3.13 to 3.47V |
| Package size | 14 x 14mm |
| RoHS | Compliant |
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These are design resources that include the Analog Devices ADSP-21562
This note explains power sequencing for ADSP-2156x processors to mitigate indeterminate I/O voltage glitches during power-up by ramping VDD_REF before VDD_EXT.
