SHARC+ single-core digital signal processor provides up to 800 MHz operation with 640 KB of L1 SRAM and 512 KB of shared L2 SRAM. The processor supports 32-bit fixed-point and 32-bit, 40-bit, and 64-bit floating-point operation for high-performance audio and signal-processing workloads. Integrated peripherals include eight SPORT interfaces, two S/PDIF receiver/transmitters, eight ASRC pairs, four I2C ports, two UARTs, quad SPI and octal SPI interfaces, timers, watchdogs, a thermal sensor, and a two-channel 12-bit housekeeping ADC. The device is supplied in a 14 mm by 14 mm 120-lead LQFP_EP package with RoHS-compliant construction and production lifecycle status.
Checking distributor stock and pricing after the page loads.
Sign in to ask questions about the Analog Devices ADSP-21563 datasheet using AI. Get instant answers about specifications, features, and technical details, ideal for finding information in larger documents.
Sign In to ChatWidest selection of semiconductors and electronic components in stock and ready to ship ™
| Core architecture | SHARC+ single-core SIMD DSP |
| Maximum core clock | 800MHz |
| L1 SRAM | 640kB |
| L2 SRAM | 512kB |
| Floating-point support | 32, 40, 64bit |
| Fixed-point support | 32bit |
| Full SPORT interfaces | 8 |
| S/PDIF receiver/transmitters | 2 |
| ASRC pairs | 8 |
| Precision clock generators | 4 |
| I2C ports | 4 |
| UARTs | 2 |
| Quad SPI interfaces | 2 |
| Octal SPI interfaces | 1 |
| Housekeeping ADC | 2-channel, 12-bit |
| GPIO pins | 22 |
| DAI pins | 24 |
| Internal core supply voltage | 0.95 to 1.05V |
| External I/O supply voltage | 3.13 to 3.47V |
| Package body size | 14 x 14mm |
| Available junction temperature ranges | -40 to +125 or 0 to +110°C |
| RoHS | Compliant |
Download the complete datasheet for Analog Devices ADSP-21563 to view detailed technical specifications.
The embedded preview will load automatically when this section scrolls into view.
These are design resources that include the Analog Devices ADSP-21563
This note explains power sequencing for ADSP-2156x processors to mitigate indeterminate I/O voltage glitches during power-up by ramping VDD_REF before VDD_EXT.
