Single-core SHARC+ digital signal processor provides up to 1 GHz operation for high-performance audio and floating-point applications. The processor integrates 640 KB of L1 SRAM with parity and 1024 KB of shared L2 SRAM with ECC protection. Peripheral resources include a 16-bit DDR3/DDR3L controller, eight full SPORT interfaces, two S/PDIF receive/transmit blocks, eight ASRC pairs, six I2C interfaces, three UARTs, and SPI, Quad SPI, and Octal SPI ports. The 400-ball CSP_BGA package measures 17 mm by 17 mm with 0.8 mm pitch and is RoHS compliant.
Checking distributor stock and pricing after the page loads.
Sign in to ask questions about the Analog Devices ADSP-21569 datasheet using AI. Get instant answers about specifications, features, and technical details, ideal for finding information in larger documents.
Sign In to ChatWidest selection of semiconductors and electronic components in stock and ready to ship ™
| Processor core | SHARC+ single core |
| Maximum core clock frequency | 1000MHz |
| L1 SRAM | 640KB |
| L2 SRAM | 1024KB |
| Floating-point support | 32, 40, 64bit |
| Fixed-point support | 32bit |
| External memory interface | 16-bit DDR3/DDR3L controller |
| SPORT interfaces | 8 full SPORT with TDM and I2S modes |
| S/PDIF interfaces | 2 receive/transmit blocks |
| ASRC channels | 8pairs |
| I2C interfaces | 6 |
| UART interfaces | 3 |
| SPI interfaces | 1 SPI, 2 Quad SPI, 1 Octal SPI |
| Link ports | 2 |
| GPIO and DAI pins | 40 GPIO, 28 DAIpins |
| Housekeeping ADC | 4-channel, 12-bit, up to 1 MSPS |
| Core supply voltage | 0.95 to 1.05V |
| I/O supply voltage | 3.13 to 3.47V |
| RoHS | Compliant |
| Automotive Qualification | AEC-Q100 qualified for automotive applications |
Download the complete datasheet for Analog Devices ADSP-21569 to view detailed technical specifications.
The embedded preview will load automatically when this section scrolls into view.
These are design resources that include the Analog Devices ADSP-21569
This note explains power sequencing for ADSP-2156x processors to mitigate indeterminate I/O voltage glitches during power-up by ramping VDD_REF before VDD_EXT.
