Embedded processor integrates a Blackfin core with dual 16-bit MACs, 40-bit ALUs, SIMD multimedia support, and dynamic power management. The device supports up to 350 MHz instruction rate, 1.0 V to 1.6 V core operation, and 3.3 V I/O. On-chip memory includes 16 KB instruction L1 SRAM/cache, 32 KB data L1 SRAM/cache, 4 KB scratchpad L1 SRAM, and 256 KB L2 SRAM. Integrated peripherals include PCI 2.2, USB 1.1 device interface, two UARTs, two SPI-compatible ports, two SPORTs, timers, watchdog, real-time clock, and programmable flag I/O. The family is supplied in a 260-ball PBGA package with commercial and industrial temperature options.
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| Processor core frequency | 350 maxMHz |
| Architecture family | Blackfin Micro Signal Architecture |
| Instruction L1 memory | 16 SRAM/cacheKB |
| Data L1 memory | 32 SRAM/cacheKB |
| Scratchpad L1 memory | 4KB |
| L2 SRAM | 256KB |
| Total on-chip memory | 308KB |
| Core supply voltage | 0.95 to 1.65 recommended, order-code dependentV |
| I/O supply voltage | 3.15 to 3.45V |
| PCI interface | 32-bit, 33 MHz, PCI 2.2 compliant master/slave |
| USB interface | USB 1.1 compliant device |
| UART ports | 2, one with IrDA |
| SPI ports | 2 |
| Synchronous serial ports | 2 full-duplex SPORTs |
| Timer/counters | 4 total, 3 with PWM support |
| Programmable flag I/O | 16pins |
| Commercial ambient temperature | 0 to 70°C |
| Industrial ambient temperature | -40 to 85°C |
| Package | 260-ball metric PBGA |
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