Blackfin embedded processor combines a dual-MAC signal-processing engine with a RISC-like instruction set and SIMD multimedia capabilities. The processor family supports core operation from 0.8 V to 1.2 V with on-chip voltage regulation and 2.5 V or 3.3 V tolerant I/O. Integrated peripherals include a 10/100 Ethernet MAC, CAN 2.0B, SPI, TWI, two UARTs, SPORT serial ports, timers, RTC, watchdog, and JTAG debug. External memory support covers SDRAM and asynchronous 8-bit or 16-bit memories, with flexible booting from flash, SPI, TWI, or UART host devices. MBGA package options are defined for the family.
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| Processor family | Blackfin |
| Maximum core frequency | 600MHz |
| Core supply voltage | 0.8 to 1.2V |
| I/O voltage tolerance | 2.5 and 3.3V |
| On-chip memory | Up to 132Kbyte |
| Ethernet interface | IEEE 802.3 10/100 Ethernet MAC |
| CAN interface | CAN 2.0B |
| UART interfaces | 2 with IrDA support |
| Synchronous serial ports | 2 dual-channel full-duplex SPORTs |
| SPI interface | SPI-compatible |
| Two-wire interface | TWI controller |
| Timer counters | 8 32-bit timer/counters with PWM support |
| GPIO count | 48 |
| Peripheral DMA channels | 12 |
| Package options | 182-ball and 208-ball MBGA |
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