Mixed-signal control processor combines a 240 MHz Arm Cortex-M4 core with floating-point support and a 100 MHz Arm Cortex-M0 supervisor core. Integrated memory includes zero-wait-state ECC SRAM and high-performance ECC flash for embedded motor-control and power-conversion applications. The analog subsystem includes a low-latency multi-channel front end with 16-bit SAR ADC capability and a 12-bit DAC. Peripheral resources include an asynchronous static memory controller, enhanced precision PWM channels, SINC filters for sigma-delta modulators, and a hardware harmonic analysis engine.
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| Core architecture | Arm Cortex-M4 with floating-point unit and Arm Cortex-M0 |
| Maximum Cortex-M4 core frequency | 240MHz |
| Maximum Cortex-M0 core frequency | 100MHz |
| Main SRAM | 160 zero-wait-state ECCKB |
| Supervisor SRAM | 32 zero-wait-state ECCKB |
| Flash memory | 512 high-performance ECCKB |
| Analog front end channels | 24channels |
| ADC dynamic performance | 11+ENOB |
| Primary ADC type | Up to two 16-bit SAR-type ADCs |
| DAC resolution | 12bit |
| Power supply | 3.3 single supplyV |
| External memory interface | Static memory controller supporting 8-bit and 16-bit asynchronous memories |
| PWM channels | 24 enhanced precision PWMchannels |
| SINC filters | Four 3rd- or 4th-order filters for sigma-delta modulators |
| Operating temperature range | -40 to 105°C |
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