High performance fanout clock buffer distributes ultralow phase noise references for high speed data converters with parallel or JESD204B serial interfaces. The device provides 14 configurable low noise outputs that can generate up to seven DCLK and SYSREF clock pairs. Clock outputs support CML, LVDS, LVPECL, and LVCMOS signaling with independent frequency and phase adjustment on each channel. Operation uses 3.3 V supplies over a −40°C to +85°C ambient temperature range in a 48-lead 7 mm × 7 mm LFCSP package.
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| Device type | Fanout clock buffer |
| Output channels | 14 |
| Maximum clock output frequency | 3200MHz |
| Maximum clock input frequency with divide by 2 | 6000MHz |
| Fundamental clock input frequency range | 200 to 3200MHz |
| Supply voltage | 3.135 to 3.465V |
| Ambient temperature range | -40 to +85°C |
| RMS additive jitter at 2457.6 MHz | <15fs rms |
| RMS additive jitter at 983.04 MHz | <30fs rms |
| Phase noise floor at 983.04 MHz | -155.2 at 20 MHz offsetdBc/Hz |
| Clock output pair skew | 15 typicalps |
| Any output pair skew | 30 typicalps |
| Output divider range | 1 to 4094 |
| Analog fine delay resolution | 25ps |
| SPI bus frequency | 10MHz |
| Package | 48-lead 7 mm x 7 mm LFCSP |
| RoHS | Compliant |
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