High performance dual-loop integer-N jitter attenuator generates low phase noise clocks for high speed data converters and JESD204B interfaces. The device provides up to 14 configurable DCLK and SYSREF outputs supporting CML, LVDS, LVPECL, and LVCMOS signaling. Integrated PLLs, selectable on-chip VCOs, holdover, loss-of-signal detection, hitless reference switching, SPI control, and GPIO alarm/status functions support clock-tree management. Typical integrated rms jitter is 44 fs from 12 kHz to 20 MHz at 2457.6 MHz, and the package is a 68-lead 10 mm × 10 mm LFCSP.
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| Function | Dual-loop integer-N jitter attenuator |
| Maximum clock output frequency | 3200MHz |
| Number of clock outputs | 14 |
| Output signaling standards | CML, LVDS, LVPECL, LVCMOS |
| RMS jitter | 44 typ at 2457.6 MHz, 12 kHz to 20 MHzfs |
| Noise floor | -156 at 2457.6 MHzdBc/Hz |
| Phase noise | -141.7 at 800 kHz offset, 983.04 MHz outputdBc/Hz |
| Reference inputs | Up to 4 LVDS, LVPECL, CMOS, or CML input clocks |
| PLL1 reference input frequency | 0.00015 to 800MHz |
| PLL2 external VCO frequency | 400 to 3200 fundamental, 400 to 6000 with divide-by-2MHz |
| On-chip VCO tuning range | 2400 to 3200 guaranteed coverageMHz |
| Clock output divider range | 1 to 4094 |
| Analog fine delay range | 135 to 670ps |
| Analog fine delay resolution | 25ps |
| SPI bus frequency | 10MHz |
| Supply voltage | 3.3 ±5%V |
| Ambient temperature range | -40 to +85°C |
| Typical total current | 586mA |
| Package | 68-lead, 10 mm × 10 mm LFCSP |
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