Tri‑Mode storage I/O controller with 16 PCIe 3.1 lanes and 16 device ports supporting SAS (12/6/3 Gb/s), SATA (6/3 Gb/s) and PCIe/NVMe (8/5/2.5 GT/s). Based on Fusion‑MPT architecture with ARM A15 @ 1.2 GHz, 6 MB on‑chip memory and 1 MB L2 cache. Supports up to 2,000 SAS/SATA devices, up to 16 direct‑attached PCIe devices, DataBolt bandwidth aggregation, EEDP, SSP/SMP/STP/SATA protocols, SAS 2.1 power management, and debug/management interfaces (I2C, UART, Ethernet, SGPIO, JTAG).
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Technical Specifications
Broadcom SAS3616W technical specifications.
General
| Host interface | PCIe 3.1 x16 (supports x16/x8/x4/x2 lanes) |
| PCIe link rate (host) | 8.0 (backward compatible to 5.0 and 2.5)GT/s per lane |
| Device ports | 16 (Tri‑Mode: SAS/SATA/PCIe)ports |
| SAS data rates | 12, 6, 3Gb/s per lane |
| SATA data rates | 6, 3Gb/s per lane |
| PCIe/NVMe device link rates | 8, 5, 2.5GT/s |
| Max SAS/SATA devices | Up to 2000devices |
| Max direct‑attached PCIe devices | Up to 16 (behind a switch also supported)devices |
| Aggregate Tri‑Mode PHY bandwidth | 19.2 (x16 Tri‑Mode PHY)GB/s |
| Host PCIe bandwidth | 16.0 (x16 PCIe 3.0 effective)GB/s |
| On‑chip CPU | ARM Cortex‑A15 @ 1.2 GHz |
| On‑chip memory | 6 (with 1 MB L2 cache)MB |
| IOPS capability | >1,000,000IOPS |
| Protocol support | SSP, SMP, STP, SATA; T10 EEDP |
| Features | DataBolt bandwidth aggregation; Spread Spectrum Clocking; PCIe AER/ECRC; SRIS; hot‑plug |
| Power management | SAS 2.1 slumber/partial; programmable SAS link power‑down; variable PCIe bandwidth negotiation |
| External memory interface | SPI Flash ROM |
| Communication/debug interfaces | I2C, UART, Ethernet (debug), SGPIO; JTAG |
| Package size | 28 (estimated)mm |
Datasheet
Broadcom SAS3616W Datasheet
Download the complete datasheet for Broadcom SAS3616W to view detailed technical specifications.
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