Cypress
CY7C341B-25JXI
CPLD MAX® Family 3.75K Gates 192 Macro Cells 50MHz 0.65um (CMOS) Technology 5V 84-Pin PLCC
PackagePLCC
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Technical Specifications
Cypress CY7C341B-25JXI technical specifications.
General
| Package/Case | PLCC |
Compliance
| RoHS | Compliant |
Datasheet
Cypress CY7C341B-25JXI Datasheet
Download the complete datasheet for Cypress CY7C341B-25JXI to view detailed technical specifications.
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