Cypress
CY7C346-35JXI
CPLD MAX® Family 2.5K Gates 128 Macro Cells 0.8um (CMOS) Technology 5V 84-Pin PLCC
PackagePLCC
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Technical Specifications
Cypress CY7C346-35JXI technical specifications.
General
| Package/Case | PLCC |
Compliance
| RoHS | Compliant |
Datasheet
Cypress CY7C346-35JXI Datasheet
Download the complete datasheet for Cypress CY7C346-35JXI to view detailed technical specifications.
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