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Application NoteNxp

AES Encryption/Decryption Using RT5xx Application Note

This application note describes how to configure and use the AES engine within the RT5xx HASH-Crypt IP for runtime encryption and decryption using the NXP SDK and PUF technology.

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Overview

This document provides a technical guide for implementing AES encryption and decryption on NXP RT5xx microcontrollers. It focuses on the HASH-Crypt IP, which includes an AES engine supporting 128-bit, 192-bit, and 256-bit keys in ECB, CBC, and CTR modes, as well as 128-bit ICB mode for side-channel protection. The note details key management options, including software-supplied keys or secret keys derived from One-Time Programmable (OTP) memory and the Physically Unclonable Function (PUF). It covers low-level peripheral initialization, data movement strategies using the AHB Master or DMA, and high-level implementation using the NXP RT595 SDK API. Practical examples are provided for the MIMXRT595-EVK development board across MCUXpresso, Keil, and IAR IDEs.

Use Cases

  • Securing data stored in non-volatile memory for application recovery
  • Encrypting and decrypting sensitive data stored in RAM during runtime
  • Establishing secure communication channels between devices with encrypted messaging
  • Managing hardware-based secret keys via OTP or PUF for enhanced security
  • Accelerating cryptographic operations using hardware-based AES engines

Topics

NXP
RT5xx
MIMXRT595
HASH-Crypt
AES engine
PUF
Physically Unclonable Function
encryption
decryption
ECB
CBC
CTR

Referenced Parts

MIMXRT595SFVKB

NXP

The board contains an NXP MIMXRT595SFVKB device which contains a 200 MHz Arm® Cortex®-M33 CPU and a 200 MHz Cadence® Tensilica® Fusion F1.

RT595

NXP

The NXP RT595 SDK includes peripheral libraries, configuration tools, documentation, and application examples using the SDK

AES Encryption/Decryption Using RT5xx Application Note | Design Resources