AN11084: Very large I2C-bus systems and long buses

Overview

This application note provides design strategies for implementing I2C-bus systems over long distances and with a high number of nodes, potentially reaching thousands. It explains how to use 'zero offset' bus buffers such as the NXP PCA9605 to divide long buses into shorter segments, regenerating clean logic signals to eliminate accumulated noise. The document addresses signal propagation delays and timing skew caused by numerous buffers and long cables, proposing hardware-based timing delay modules for both master and slave nodes. It compares I2C implementations to RS-485 and CAN bus for multi-drop architectures using Cat5 or Cat6 cabling.

Referenced Parts