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Application NoteNxp

AN13152: SHA Engine Usage and Configuration on RT500

This application note details the configuration and performance of the SHA engine on NXP RT500 MCUs, supporting SHA-1 and SHA-256 with hardware acceleration.

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Overview

This document provides a technical overview of the HASH-AES block within the NXP RT500 (RT5xx) series microcontrollers, specifically focusing on the SHA engine. It covers the hardware implementation of SHA-1 and SHA-256 algorithms, detailing initialization steps, AHB master mode configuration, and interrupt handling. The note explains how the engine processes 512-bit blocks in 80 cycles (SHA-1) or 64 cycles (SHA-256). It also includes documentation for the fsl_hashcrypt SDK drivers, performance analysis for CPU, DMA, and AHB-led data loading, and instructions for using the demonstration application on the MIMXRT595EVK evaluation board.

Use Cases

  • Secure boot code integrity verification
  • Digital signature model implementation
  • Hash-based Message Authentication Code (HMAC) validation
  • Challenge/response security protocols
  • Memory block compromise detection

Topics

NXP
RT500
MIMXRT595S
SHA-256
SHA-1
HASH-AES
Cryptography
Hardware Acceleration
HMAC
fsl_hashcrypt
AHB Master

Referenced Parts

MIMXRT595S

NXP Semiconductors

The below mentioned APIs are defined & declared in fsl_hashcrypt.c/.h inside the SDK (SDK/devices/MIMXRT595S/drivers)

MIMXRT595

NXP Semiconductors

Open the MIMXRT595S_cm33_features.h file (present inside device folder inside mdbedtls_benchmark project inside each IDE)

RT500

NXP Semiconductors

This application note introduces users with the usage and configuration of SHA engine on RT500.

AN13152: SHA Engine Usage and Configuration on RT500 | Design Resources