MC68360
NXP
three MC68360 may be interfaced together, one in master mode and two in slave mode
Application NoteNxp
AN2032: Multi-QUICC System Design
Application note detailing how to interface multiple MC68360 communications controllers in a master-slave configuration to increase available serial channels.
Overview
This document provides a design concept for interfacing multiple NXP MC68360 (QUICC) integrated communications controllers to expand high-speed serial communication capacity. It specifically describes a three-device system consisting of one master and two slaves. The guide covers hardware interfacing requirements, including data and address bus routing, bus arbitration logic, system clocking, and reset synchronization. Furthermore, it details the software procedures for relocating the Module Base Address Register (MBAR) via keyed writes and managing interrupt processing across multiple devices using the IRQOUT and autovectoring capabilities.
Use Cases
- Increasing high-speed serial communication channels in telecommunications equipment
- Designing multi-QUICC communication systems with shared bus architecture
- Expanding MC68360 SCC capacity beyond the standard four channels
- Managing interrupt vectoring in multi-processor NXP designs
Topics
NXP
MC68360
QUICC
multi-processor system
serial communication channels
SCC
bus arbitration
MBAR
interrupt handling
master-slave configuration
Referenced Parts
| MC68360 | NXP | three MC68360 may be interfaced together, one in master mode and two in slave mode |