MC68302
NXP
Interfacing the MC68360 to the MC68302
Application NoteNxp
AN2038: Interfacing the MC68360 to the MC68F302
Technical guide for interfacing NXP MC68360 and MC68F302 processors, covering bus timing discrepancies, AS signal delays, and idle cycle insertion to prevent bus contention.
Overview
This application note details hardware interface requirements and timing solutions for connecting the MC68360 (QUICC) to the MC68F302. It identifies two primary bus specification mismatches: the Address Strobe (AS) signal negation timing and data bus high-impedance transitions during read-to-write cycles. The document provides specific logic workarounds, including using 74HC series devices to introduce a signal delay and implementing bus arbitration logic to insert idle cycles. These methods prevent bus contention and ensure timing compatibility between the two processor families.
Use Cases
- Interfacing MC68360 and MC68F302 processors
- Resolving bus timing violations in 68k systems
- Implementing AS signal delay logic
- Designing multiprocessor communication interfaces
Topics
MC68360
MC68F302
MC68302
QUICC
NXP
Freescale
bus timing
Address Strobe
AS signal
bus contention
logic interfacing
Referenced Parts
MC68360
NXP
Interfacing the MC68360 to the MC68302
| MC68302 | NXP | Interfacing the MC68360 to the MC68302 |
| MC68360 | NXP | Interfacing the MC68360 to the MC68302 |