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Application NoteNxp

Boosting Application Performance with KW47 Dual-Core Architecture

This application note explains how to use the NXP KW47 dual-core architecture and Narrowband Unit (NBU) to offload tasks and improve embedded system performance.

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Overview

This document provides a technical overview of leveraging the dual-core architecture of the NXP KW47 microcontroller to enhance performance. The KW47 integrates two Arm Cortex-M33 cores: a primary core for main application processing and a secondary core located within the Narrowband Unit (NBU). While the NBU is primarily designed for the radio subsystem, it can be utilized as a general-purpose processor to handle heavy computational tasks. The note describes Inter-Processor Communication (IPC) mechanisms, including the Messaging Unit (MU) and shared SRAM (SMU2), and demonstrates a use case where Fast Fourier Transform (FFT) calculations are offloaded to the NBU to maintain system responsiveness on the main core.

Use Cases

  • Computational offloading for signal processing (FFT)
  • Bluetooth Low Energy communication frameworks
  • UI and display management multitasking
  • Real-time workload distribution in embedded systems
  • Vibration monitoring and audio analysis

Topics

AN14846
KW47
NXP
Dual-Core
Arm Cortex-M33
Narrowband Unit
NBU
Inter-Processor Communication
IPC
Messaging Unit
FFT offload

Referenced Parts

KW47

NXP

The KW47 microcontroller integrates two Arm Cortex-M33 cores, one of which resides in the Narrowband Unit (NBU).

Boosting Application Performance with KW47 Dual-Core Architecture | Design Resources