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CPM Hints for NXP MPC823 and MPC860 Communication Processor Modules

Technical guidance for the Communication Processor Module (CPM) in NXP MPC823 and MPC860 series, covering SCC configuration, buffer descriptors, SDMA behavior, and troubleshooting.

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Overview

This document provides technical implementation hints and troubleshooting procedures for the Communication Processor Module (CPM) used in NXP MPC823, MPC860, and MC68360 microcontrollers. It details the interaction between the CPU and CPM via microcode commands, buffer descriptors (BD), and event registers. The text provides a mapping of the SCC Parameter RAM, explaining the function of registers such as RBASE, TBASE, and MRBLR. Detailed walkthroughs of the transmit and receive frame processes are included to help developers verify clocking, SDMA arbitration, and FIFO operations. Additionally, the document addresses performance optimization, highlighting the impact of opening and closing buffer descriptors on bus latency, and describes SDMA cycle-stealing behavior across different bus widths.

Use Cases

  • Troubleshooting SCC communication issues in PowerQUICC processors
  • Configuring buffer descriptors for data transmission and reception
  • Debugging SDMA arbitration and priority settings
  • Optimizing CPM performance for high-load communication tasks
  • Verifying clocking and physical interface configurations

Topics

NXP MPC823
NXP MPC860
NXP MPC860SAR
NXP MC68360
CPM
SCC
Buffer Descriptors
SDMA
Parameter RAM
Microcode
Serial Communications Controller
RISC

Referenced Parts

MPC823

NXP

Source URL: https://www.nxp.com/docs/en/application-note/MPC823CPM.pdf

MPC860

NXP

The only bursts are from the IDMAs on the MPC860

MC68360

NXP

instead it was decided to be exactly compatible with the 68360.

MPC860SAR

NXP

ATM protocols on the 860sar.