K32L3A6
NXP
The K32L3A6 is an asymmetric dual-core device (with two different cores as opposed to symmetric dual-core devices which have identical cores that operate in lockstep) containing an Arm® Cortex®-M4 core and an Arm Cortex-M0+ core.
Application NoteNxp
Dual-core Project Creation and Conversion for K32L3A6 Devices
Technical guide for developing dual-core applications on NXP K32L3A6 MCUs using IAR and MCUXpresso IDEs, covering project setup, linker configuration, and multicore debugging.
Overview
This application note provides detailed instructions for creating, configuring, and converting multi-core projects for the K32L3A6 asymmetric dual-core microcontroller. The device features an Arm Cortex-M4 primary boot core and an Arm Cortex-M0+ secondary core. The document explains the architectural relationship between cores, including peripheral access via AXBS0 and AXBS1 crossbars and common utilities like the SEMA42 and Messaging Unit (MU). It offers step-by-step workflows for IAR and MCUXpresso IDEs, focusing on linker settings for secondary core binary placement, memory mapping, and establishing simultaneous multicore debug connections.
Use Cases
- Developing dual-core firmware for K32L3A6 microcontrollers
- Converting existing single-core projects to dual-core architectures
- Configuring IDE linker files for secondary core image placement
- Setting up simultaneous debug environments for M4 and M0+ cores
Topics
K32L3A6
Cortex-M4
Cortex-M0+
Dual-core MCU
IAR Embedded Workbench
MCUXpresso IDE
Multicore debugging
Linker configuration
Asymmetric dual-core
NXP Kinetis
Referenced Parts
| K32L3A6 | NXP | The K32L3A6 is an asymmetric dual-core device (with two different cores as opposed to symmetric dual-core devices which have identical cores that operate in lockstep) containing an Arm® Cortex®-M4 core and an Arm Cortex-M0+ core. |