MSC8157
NXP
This errata describes corrections to the MSC8157 Reference Manual, Revision 2.
Design DocumentNxp
Errata for MSC8157 Reference Manual (MSC8157RMAD)
This addendum provides corrections and updates to the MSC8157 Reference Manual, specifically focusing on SerDes register definitions and reset configuration descriptions.
Overview
This document (MSC8157RMAD Rev. 2.1) serves as an errata addendum to the MSC8157 Reference Manual. It details critical corrections for register figures and bit descriptions, including the SerDes Bank 1 Reset Control Register (SRDSB1RSTCTL) and Lane A–J General Control Register 0 (L[A–J]GCR0). Key updates include the definition of reset status bits (RST_DONE, RST_ERR), receiver/transmitter reset bits (RRST, TRST), and speed selection fields (RRAT_SEL, TRAT_SEL). These changes ensure accurate configuration of the multicore DSP's SerDes lanes and reset logic.
Use Cases
- Updating software drivers to match corrected SerDes register definitions
- Implementing correct SerDes reset sequences for MSC8157 hardware
- Configuring transmitter and receiver lane speeds in multicore DSP applications
- Validating hardware register configurations against the latest device documentation
Topics
NXP
MSC8157
Freescale
Errata
SerDes
SRDSB1RSTCTL
L[A-J]GCR0
Reference Manual Addendum
DSP
Register Map
Referenced Parts
| MSC8157 | NXP | This errata describes corrections to the MSC8157 Reference Manual, Revision 2. |