i.MX51
Freescale Semiconductor
i.MX51 Multimedia Applications Processor Reference Manual
Design DocumentNxp
Errata to i.MX51 Multimedia Applications Processor Reference Manual
Addendum providing corrections to the i.MX51 Reference Manual, including system memory map updates and High-Speed Communication (HSC) architecture details.
Overview
This document serves as an errata and addendum to the i.MX51 Multimedia Applications Processor Reference Manual (Revision 1). It includes critical updates to the system memory map for the AIPS_TZ#2 region and introduces comprehensive technical details regarding High-Speed Communication (HSC) functionality. The HSC section describes the IPUv3EX architecture for camera and display port configurations, including CSI-2 and DSI translators. Technical data includes memory map offsets, bypass register settings for MCD, MCCMC, and MXT_CONF, and descriptions of the TRIPPI physical layer protocol interface.
Use Cases
- System memory map verification for i.MX51 software development
- Configuring High-Speed Communication (HSC) bridges for camera and display interfaces
- Implementing legacy mode bypass for IPUv3EX interfaces
- Register-level configuration of CSI-2 and DSI translators
Topics
i.MX51
Freescale Semiconductor
NXP
Multimedia Applications Processor
Reference Manual Errata
High-Speed Communication
HSC
CSI-2 Translator
DSI Translator
IPUv3EX
Memory Map
Referenced Parts
| i.MX51 | Freescale Semiconductor | i.MX51 Multimedia Applications Processor Reference Manual |