MSC8157E
Freescale Semiconductor
This errata describes corrections to the MSC8157E Reference Manual, Revision 2.
Design DocumentNxp
Errata to MSC8157E Reference Manual, Rev. 2
This addendum provides technical corrections for the MSC8157E Reference Manual, focusing on register bit descriptions for SerDes reset control and lane general control registers.
Overview
This design document serves as a formal addendum to Revision 2 of the MSC8157E Reference Manual. It details critical corrections across several sections, specifically updating register figures and field descriptions for the SerDes Bank 1 Reset Control Register (SRDSB1RSTCTL) and Lane A–J General Control Registers (L[A–J]GCR0). Key updates include the correction of bit assignments for reset status (RST_DONE, RST_ERR) and lane reset signals (RRST, TRST), as well as receiver and transmitter speed selection settings. The document also clarifies RCWLR register descriptions and updates exception modes for hardware configuration.
Use Cases
- Correcting register definitions in software drivers for the MSC8157E processor.
- Debugging SerDes PLL lock and reset sequence issues in high-speed communication interfaces.
- Verifying hardware configuration modes and transmitter/receiver speed selections.
- Ensuring accurate hardware initialization during the system boot process.
Topics
MSC8157E
Freescale
NXP
Errata
Reference Manual
SerDes
SRDSB1RSTCTL
L[A-J]GCR0
RCWLR
Register Mapping
Reset Control
Referenced Parts
| MSC8157E | Freescale Semiconductor | This errata describes corrections to the MSC8157E Reference Manual, Revision 2. |