ESP32-C3
Espressif Systems
ESP32-C3 TRM (Pre-release v0.6)
Design DocumentRaw Githubusercontent
ESP32-C3 Series Technical Reference Manual
A comprehensive technical reference manual for the Espressif ESP32-C3 RISC-V SoC, detailing CPU architecture, memory mapping, peripherals, and security features.
Overview
This technical reference manual provides in-depth documentation for the ESP32-C3 series of SoCs from Espressif Systems. It covers the ESP-RISCV CPU core, including its register sets and interrupt controller. Detailed chapters explore the system architecture, memory map, GDMA controller, and IO MUX/GPIO matrix. The document also describes essential system functions like clock management, low-power modes, and various timers such as SYSTIMER, TIMG, and Watchdog Timers. Furthermore, it provides technical specifications for hardware security accelerators including SHA, AES, RSA, HMAC, and digital signature modules, alongside standard peripherals like UART and the Random Number Generator (RNG).
Use Cases
- IoT device development
- Firmware engineering
- Hardware-level programming
- Secure system design
- Peripheral driver development for ESP32-C3
Topics
ESP32-C3
RISC-V
Espressif Systems
Technical Reference Manual
Microcontroller
SoC
GDMA
GPIO Matrix
Security Accelerators
AES
SHA
RSA
Referenced Parts
ESP32C3
Espressif Systems
PRELIMINARY ESP32C3 Technical Reference Manual
| ESP32-C3 | Espressif Systems | ESP32-C3 TRM (Pre-release v0.6) |
| ESP32C3 | Espressif Systems | PRELIMINARY ESP32C3 Technical Reference Manual |