MC68360
Motorola
The MC68360 Quad Integrated Communications Controller (QUICC) has many seven controllers and it is often important to evaluate the maximum serial performance
Application NoteNxp
Evaluating the MC68360 Serial Performance
Technical guide and software routines for evaluating the serial performance and Communication Processor (CP) loading of the MC68360 QUICC under various traffic configurations.
Overview
This application note provides a methodology for testing the maximum serial performance of the MC68360 Quad Integrated Communications Controller (QUICC). It explains how the Communication Processor (CP) prioritizes tasks across four Serial Communication Controllers (SCCs), two Serial Management Controllers (SMCs), and a Serial Peripheral Interface (SPI). The document details a performance testing technique using RISC timers compared against hardware timers to detect CP saturation and potential data loss. It includes specific software routines (PERFINIT, CHKPERF, and SCCINIT) for use on the QUADS development board to simulate high-traffic HDLC applications and evaluate system stability at various baud rates.
Use Cases
- Simulating worst-case serial traffic patterns
- Evaluating CP utilization in multi-channel systems
- Detecting serial FIFO underrun or overrun conditions
- Optimizing baud rate configurations for serial controllers
- Benchmarking communications processor performance
Topics
MC68360
QUICC
Serial Communication Controller
SCC
Communication Processor
CP Load
HDLC
RISC Timers
QUADS development board
Baud Rate Generator
Serial Performance
Referenced Parts
| MC68360 | Motorola | The MC68360 Quad Integrated Communications Controller (QUICC) has many seven controllers and it is often important to evaluate the maximum serial performance |