LPC55S16
NXP
The hardware uses LPCXpresso55S16 board, as shown in Figure 7.
Application NoteNxp
Firmware Update Using Secondary Bootloader on LPC55xx
Implementation guide for a dual-image secondary bootloader on NXP LPC55xx MCUs to ensure reliable firmware updates using MCUBOOT protocol and UART communication.
Overview
This application note describes the implementation of a Dual image Secondary Boot Loader (DSBL) for the NXP LPC55xx microcontroller series, specifically targeting the LPC55S69 and LPC55S16. Because the native ROM bootloader does not natively support dual-image redundancy, this document provides a method to ensure reliable firmware updates by utilizing two flash regions: a Receive Region for new downloads and a Main Region for the bootable image. The DSBL performs integrity checks and version comparisons before copying images to the Main Region. The implementation uses the NXP MCUBOOT protocol for communication via UART and is compatible with the blhost PC command-line tool. Technical details include the application image format, memory layout, image header structures with CRC32 verification, and step-by-step demo instructions for LPC55xx evaluation kits.
Use Cases
- Implementing reliable firmware update mechanisms with rollback capability
- Developing secondary bootloaders for NXP LPC5500 series microcontrollers
- Integrating MCUBOOT protocol into custom embedded applications
- Managing dual-bank flash memory for secure boot and application updates
Topics
LPC55xx
LPC55S69
LPC55S16
Secondary Bootloader
Dual Image Update
MCUBOOT
blhost
Firmware Update
CRC32
UART
Flash Partitioning
Referenced Parts
LPC55S69
NXP
It takes LPC55S69 as example, and other LPC5500 series follow similar steps.
| LPC55S16 | NXP | The hardware uses LPCXpresso55S16 board, as shown in Figure 7. |
| LPC55S69 | NXP | It takes LPC55S69 as example, and other LPC5500 series follow similar steps. |