Skip to main content
Datasheets.com
Application NoteNxp

i.MX RT700 Deep Sleep and Wake-up Time Application Note

Technical guide for configuring Deep Sleep and Async Deep Sleep modes on NXP i.MX RT700 MCUs, including power domain management, voltage requirements, and wake-up latency.

View application note

Overview

This application note provides a technical overview of low-power management for the NXP i.MX RT700 crossover MCU, specifically focusing on Deep Sleep and Asynchronous Deep Sleep modes. It details the device's segmented power architecture, which features independent Compute and Sense domains controlled via SLEEPCON and Power Management Controller (PMC) registers. The document specifies minimum voltage requirements for VDD1, VDD2, and VDDN rails during different sleep states and compares wake-up sources, such as RTC and GPIO, against wake-up latency. It also covers the integration of the NXP PCA9422 PMIC for power delivery and provides guidance on using SDK examples for dual-core power mode synchronization and measurement.

Use Cases

  • Optimizing power consumption in battery-operated IoT and portable electronics.
  • Configuring asynchronous wake-up sources such as RTC alarms or GPIO edge detection.
  • Managing independent power domains for Compute and Sense cores in multi-core applications.
  • Implementing PMIC-controlled power delivery for i.MX RT700 based system designs.

Topics

i.MX RT700
NXP PCA9422
Deep Sleep Mode
Async Deep Sleep
Power Management
Wake-up Latency
Low Power MCU
PMC Configuration
SRAM Retention
RT700 SDK

Referenced Parts

PCA9422

NXP

The MIMXRT700-EVK integrates NXP’s PCA9422 PMIC, which supports configurable ramp-up speeds for voltage rails.

i.MX RT700

NXP

The i.MX RT700 features a segmented power architecture with nine independent power domains and multiple voltage rails.

RT700

NXP

Latency, Power Management, NXP RT700 SDK, SRAM Retention, PMC Configuration, PCA9422