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Application NoteNxp

i.MX51 DDR/mDDR Calibration Procedure

Calibration procedure for optimizing DQS delay line settings for i.MX51 processors interfacing with Mobile DDR and DDR2 memory.

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Overview

This application note provides a detailed calibration procedure to determine optimal delay line settings for the i.MX51 multimedia processor when interfacing with Mobile DDR (mDDR) or DDR2 memories. The goal is to align DQS (data query strobe) edges to the midpoint of the data window for reliable read and write operations. The document explains the functionality of the ESDCTLv2 memory controller, specifically focusing on the ESDCDLY1-5 registers which control physical delay units. It outlines the specific steps for DDR2 DQS gating calibration and the calculation of delay parameters to compensate for process, voltage, and temperature (PVT) variations. Instructions include using a check function in internal memory to validate delay settings across different address spaces and data bytes.

Use Cases

  • DDR2 and mDDR memory interface design
  • Optimizing memory controller timing for PVT variations
  • Hardware board bring-up for i.MX51 based systems
  • Determining DQS gating parameters for DDR2 on-die termination

Topics

NXP
i.MX51
DDR2
mDDR
DQS calibration
ESDCTLv2
delay line settings
memory controller
MCIMX51
timing alignment

Referenced Parts

MCIMX51

NXP

MCIMX51 Multimedia Applications Processor Reference Manual

i.MX51

NXP

optimal delay line settings for the i.MX51

i.MX51 DDR/mDDR Calibration Procedure | Design Resources