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Application NoteNxp

i.MX51 – Modifying WinCE 6.0™ Bootloader and Kernel for Alternate SDRAM Support

Instructions for modifying the i.MX51 WinCE 6.0 BSP bootloader and kernel to support custom SDRAM hardware and timing parameters instead of the default EVK configuration.

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Overview

This application note describes the process of adapting the Windows Embedded CE 6.0 (WinCE) Board Support Package (BSP) for the NXP i.MX51 processor to support alternate SDRAM devices. It focuses on configuring the Enhanced Synchronous Dynamic Random Access Memory Controller (ESDRAMC), also referred to as eSDCTL. The document details key configuration registers including ESDCTL0/1, ESDCFG0/1, and ESDMISC. It provides guidance on setting parameters such as row and column address width, refresh rates, and specific memory timing constants like tRFC, tXSR, and tRAS. Additionally, it references the ESDRAMC_Config_Tool.xls spreadsheet used to calculate register values from memory datasheet parameters.

Use Cases

  • Adapting i.MX51 reference designs for custom SDRAM hardware
  • Modifying WinCE 6.0 BSP for different memory timing requirements
  • Configuring the i.MX51 Enhanced SDRAM Controller registers
  • Calculating ESDRAMC register values for LPDDR or DDR2 devices

Topics

i.MX51
MCIMX51
WinCE 6.0
BSP
SDRAM
ESDRAMC
eSDCTL
LPDDR
DDR2
bootloader
kernel
memory controller

Referenced Parts

MCIMX51

Freescale Semiconductor

See MCIMX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for more detailed information on these registers.

i.MX51

Freescale Semiconductor

Software supplied in the i.MX51 application processor Windows Embedded CE 6.0TM (WinCE) board support package (BSP) is configured to support the synchronous dynamic random access memory (SDRAM) specified in the i.MX51 evaluation kit (EVK) r

i.MX51 – Modifying WinCE 6.0™ Bootloader and Kernel for Alternate SDRAM Support | Design Resources