MC68340
Motorola
MC68340 Integrated Processor With DMA User's Manual
Design DocumentNxp
MC68340 Integrated Processor with DMA User's Manual Addendum
Technical addendum for the MC68340 processor covering CPU32 operand alignment, interrupt latency, bus arbitration priority, and PLL clock configuration updates.
Overview
This technical addendum provides critical updates and clarifications for the MC68340 Integrated Processor with DMA User's Manual (Revision 1). It details specific CPU32 architecture requirements, such as word-alignment restrictions for operands and instructions. The document outlines refined timing specifications for interrupt latency, bus arbitration priority between DMA and CPU, and operand coherency during multi-cycle transfers. Technical revisions are also provided for the clock synthesizer module, including VCO block diagrams, XFC capacitor recommendations for stable PLL operation, and updated frequency programming tables for system clock configuration.
Use Cases
- Firmware development and instruction optimization for MC68340-based embedded systems.
- Hardware timing analysis for interrupt response and bus cycle termination.
- System clock design and PLL circuit stabilization using XFC capacitor values.
- Debugging bus arbitration and data coherency in multi-master system architectures.
Topics
Motorola
MC68340
MC68340FE16C
CPU32
DMA
Interrupt Latency
Bus Arbitration
PLL
VCO
MBAR
Reset Operation
Integrated Processor
Referenced Parts
MC68340FE16C
Motorola
rev C suffix product e.g. MC68340FE16C
| MC68340 | Motorola | MC68340 Integrated Processor With DMA User's Manual |
| MC68340FE16C | Motorola | rev C suffix product e.g. MC68340FE16C |