MCF5235
NXP
MCF5235 Reference Manual Addendum
Design DocumentNxp
MCF5235 Reference Manual Addendum
Technical addendum and errata for the NXP MCF5235 ColdFire microcontroller reference manual, providing corrections for registers, pinouts, and peripheral operations.
Overview
This document is an addendum to the MCF5235 Reference Manual (MCF5235RM), detailing errata and corrections for revisions 1.1 and 2 of the original documentation. It provides critical updates for the NXP MCF5235 ColdFire microcontroller, including pin location corrections for 160QFP and 196BGA packages, specifically for signals like SD_CKE and QSPI_CS1. The document clarifies register behaviors for the Chip Configuration Module (CCM), cache control (CACR/ACR), and RAMBAR. Notable technical corrections include specific handling requirements for the Fast Ethernet Controller (FEC) to prevent duplicate frame transmission, updated interrupt priority and Level IACK (LnIACK) register addresses, and revised PLL behavior descriptions during stop mode. It also includes timing diagram corrections for the DMA and SDRAM controllers.
Use Cases
- Hardware design verification for MCF5235 pin assignments
- Developing software drivers for the Fast Ethernet Controller (FEC)
- Configuring interrupt priority and handling on ColdFire V2 cores
- Debugging system clocking and low-power stop mode behavior
- Validating register bit-field definitions for system integration
Topics
MCF5235
ColdFire
NXP
Freescale
Microcontroller
Errata
FEC
PLL
Interrupt Controller
SDRAM Controller
Pinout
160QFP
Referenced Parts
| MCF5235 | NXP | MCF5235 Reference Manual Addendum |