MPC8315E
NXP
Errata to MPC8315E PowerQUICC II Pro Integrated Host Processor Family Reference Manual
Design DocumentNxp
MPC8315E PowerQUICC II Pro Integrated Host Processor Errata to Reference Manual
Errata document for the MPC8315E PowerQUICC II Pro Reference Manual detailing corrections for System PLL registers, DDR memory controller configuration, and USB interface registers.
Overview
This addendum provides technical corrections and updates to the MPC8315E PowerQUICC II Pro Integrated Host Processor Family Reference Manual (Revision 2). Key updates include the addition of the SVCOD field to the System PLL Mode Register and revisions to the DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) regarding data bus width (DBW) and burst enable (8_BE) settings. The document also contains updated block diagrams for the DDR memory controller and specific corrections for USB controller registers, including reset values for FRINDEX and PERIODICLISTBASE, and updated bit field descriptions for OTGSC and USBMODE. Clarifications are also provided for the Local Bus Controller (eLBC) regarding transfer error status reporting logic.
Use Cases
- Firmware development for MPC8315E processors
- Hardware design validation and register configuration
- DDR1/DDR2 memory interface implementation
- USB host and device controller setup
- System clocking and PLL frequency debugging
Topics
MPC8315E
NXP
Freescale
PowerQUICC II Pro
Errata
DDR SDRAM Controller
USB Controller
System PLL
eLBC
Reference Manual
Referenced Parts
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