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Design DocumentNxp

MSC8157E Reference Manual

Reference manual for the NXP MSC8157E, a six-core StarCore SC3850 DSP optimized for broadband wireless access with hardware acceleration and integrated security.

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Overview

This comprehensive reference manual provides detailed technical specifications for the NXP MSC8157E, a high-performance digital signal processor (DSP) featuring six StarCore SC3850 cores. The document describes the system architecture, including the Multi Accelerator Platform Engine for Baseband 2 (MAPLE-B2), a dedicated Security Engine (SEC), and the Chip-Level Arbitration and Switching System (CLASS). It covers memory subsystems such as L1/L2 caches and the DDR-SDRAM controller, alongside high-speed serial interfaces including Serial RapidIO, PCI Express, and the Common Public Radio Interface (CPRI). Additional sections detail the QUICC Engine subsystem for Ethernet and SPI, DMA controllers, timers, and general-purpose I/O configurations.

Use Cases

  • Broadband wireless access infrastructure
  • Baseband processing for cellular networks
  • High-speed signal processing
  • LTE and WiMAX base station design
  • Secure wireless communication systems

Topics

MSC8157E
StarCore SC3850
DSP
MAPLE-B2
Security Engine
Serial RapidIO
PCI Express
CPRI
QUICC Engine
DDR-SDRAM Controller
Baseband Processing

Referenced Parts

MSC8157E

NXP

MSC8157E Reference Manual Broadband Wireless Access Six Core DSP With Security

0x0000

Maxim

0x0000 Maximum PDU

0x40

Maxim

0x40 Maximum Transmission Unit

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes.

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes

256-byte

Maxim

• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)

256-byte

Maxim

„ 256-byte maximum payload size (MAX_PAYLOAD_SIZE).

64-Gbyte

Maxim

size may be programmed less than the 64-Gbyte maximum. However, accesses that miss all other windows